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CS621x
  • USB3.2 Gen2 and DP1.4 HBR3 Retimer。USB3.2 Gen2 and DP1.4 HBR3信号重整器, 可支持USB3.2 Gen2 10Gbps與DP1.4 HBR3 8.1Gbps。内含Jitter消除與動态自動補(bǔ)償,可以大幅度的減小對PCB布線的限制,主要用於(yú)主闆/筆電/Docks的Type-C/USB3.2端口。
産品主要特性

1. Auto Adaptive AFE/DFE for different channel loss.
2. USB: protocal-awareness USB power management.
3. DP: adaptive Link training control, LTTPR Transparent/Non-transparent.
4. Jitter clean design of retimer structure on both DP/USB path.
5. BLR repeater mode for very low signal path latency.
6. Programmable multi-tap TX FFE.
7. Crystal-less: no external crystal or reference clock is needed.
8. Build-in Eye-Opening monitor circuit (ASL own feature).
9. Low power consumption.
10. Build-in control logic for Type-C normal and flip plug orientation.
11. Embedded MCU for flexibility.